This invention relates to programmable logic array integrated circuit devices, and more particularly to programmable logic array devices having discrete programmable logic regions that are grouped together and are interconnected by three types of conductors.
Programmable logic array integrated circuits are well known as shown, for example, by commonly-assigned U.S. Pat. Nos. 5,260,610 and 5,260,611, which are hereby incorporated by reference in their entirety. As shown in those patents, many modern programmable logic array devices have a large number of programmable logic regions disposed in a two-dimensional array on the integrated circuit. Each programmable logic region is capable of performing a relatively simple logic function, the particular logic function performed by each programmable logic region being selected when the device is "programmed" prior to its use as a logic device. Interconnection conductors are provided on the device for (1) delivering to each programmable logic region the signals on which that programmable logic region will operate, and (2) conveying from each programmable logic region the signals indicative of the logic performed by that programmable logic region. These interconnection conductors can be used to convey output signals from one programmable logic region to the inputs of other programmable logic regions, thereby making it possible for the programmable logic array device to perform much more complex logic functions than any individual programmable logic region can perform. Just as the logic functions performed by the individual programmable logic regions are programmable, many of the connections between interconnection conductors and between the programmable logic regions and the interconnection conductors are also typically programmable so that the manner in which signals are routed through the interconnection conductors and the manner in which the programmable logic regions are thereby interconnected is also programmable.
It is difficult to design a programmable logic array device of the type described above which has just the right ratio of programmable logic region resources to interconnection conductor resources. These devices are intended as general-purpose devices, and the designer of a device cannot know all of the many uses to which end users may wish to put the device. For example, some uses may require a high degree of interconnection between programmable logic regions, while other uses may need much less interconnection. Even the type of interconnection needed by the user may vary. Some uses may involve functions with large fan out, requiring wide distribution of a programmable logic region output to many other programmable logic regions. Other uses may involve more incremental logic, never requiring that any programmable logic region output go to more than a small number of other programmable logic regions.
One device architecture for providing interconnection circuitry that will meet a variety of needs is shown in U.S. Pat. No. Re. 34,363, and embodied in a commercial product available from the assignee of that patent. That architecture includes many short segments of conductor, having lengths on the order of the length of one programmable logic region. Those short conductors are programmably interconnectable to route signals from one programmable logic region to one or more other programmable logic regions. Although a small number of "global" conductors--i.e., conductors that span an entire dimension of the array--are provided, most "long-distance" connections between programmable logic regions must be constructed by programmably connecting a number of short conductors. A disadvantage of this approach is that each conductor connection tends to delay and attenuate the signal being transmitted. Because the numbers of conductor connections through which various signals may have to travel can vary significantly, maintaining synchronization and uniform level among several signals can be difficult or may limit the speed at which the device can be operated. Moreover, to the extent that programming a programmable interconnection consumes a portion of the memory and programming resources of the device, constructing long-distance interconnections by programmably connecting large numbers of short conductors consumes a large amount of device resources that otherwise could be devoted to logic functions.
One of the motivations behind the architecture just described is that heretofore integrated circuit devices were primarily provided on substrates having one semiconductor layer, in which the programmable elements are formed, and two metallization layers, in which conduction paths are formed, all separated by appropriate insulating layers.
Recently, semiconductor devices having three metallization layers have become more readily available. It would be desirable to be able to provide a programmable logic array device architecture that takes advantage of the greater availability of such devices. In particular, it would be desirable to be able to provide a programmable logic array device architecture that relies on fewer programmable resources to achieve connections between programmable logic regions thereof. It would also be desirable to be able to provide such a device having a greater number of global conductors.